Avionics Switch is a specific implementation of ARINC Specification Part7, a profiled version of IEEE network per parts 1 & 2, which defines how. ARINC Data Types. The specification ARINC Specification , Part 7, Aircraft Data Network, Avionics Full Duplex Switched Ethernet (AFDX) Network defines two types of messages; Explicit and Implicit. Explicit messages contain format data to allow the receiver to interpret the data types. AFDX is described as ARINC specification part 7; The ARINC covers in general, the usage of Ethernet as an airborne communication system, extended.


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The six primary aspects arinc 664 specification an AFDX data network include full duplexredundancy, determinism, high speed performance, switched and profiled network. ARINC utilizes a unidirectional bus with a single transmitter and up to twenty receivers.

MX Foundation 4: ARINC Frames

A data word arinc 664 specification of 32 bits communicated over a twisted pair cable using the bipolar arinc 664 specification modulation. There are two speeds of transmission: Also the switch, having a VL configuration table loaded, can reject any erroneous data transmission that may otherwise swamp other branches of the network.

Additionally, there can be sub-virtual links sub-VLs that are designed to carry less critical data. Sub-virtual links are assigned to a particular virtual link.

Data are read in a round-robin sequence among the virtual links with data to transmit.

Avionics Switch

There is no specified arinc 664 specification to the number of Virtual Links that can be handled by each End System, although this will be determined by BAG rates and max frame size specified for each VL versus Ethernet data rate.

However, the number of sub-VLs that may be created in a single Virtual Link is limited to four.


The switch must also be non-blocking at data rates that are specified by the system integrator, and in practice this may arinc 664 specification that the switch shall have a switching capacity that is the sum of all of its physical ports.

This jitter may be introduced by the transmitting technology and traffic-shaping function.

Computer Science > Networking and Internet Architecture

Arinc 664 specification given ES may have arinc 664 specification transmit data for multiple VLs, so a frame from one VL can be delayed up to the maximal allowed jitter value to limit the instantaneous ES frame rate and thus accommodate frames from other VLs.

Latency Although ARINC Part 7 does not specify a maximal system latency, any supplier is required to specify the upper limit of latency for any system delivered.


The specification does set down limits for some aspects of system latency. To reduce latency ENET can arinc 664 specification its Fragmentation option that reduces latency between packet in scheduling scenario.

AFDX Analyzer Software » TechSAT

In one abstraction, it is possible to visualise the VLs as an ARINC style network each with one source and one or more arinc 664 specification. Virtual links are unidirectional logic paths from arinc 664 specification source end-system to all of the destination end-systems.

The virtual link ID is a bit unsigned integer value that follows a constant bit field.

The switches are designed to route an incoming arinc 664 specification from one, and only one, end system to a predetermined set of end systems. Finally, we conduct the performance analysis of such a proposal on a realistic AFDX configuration.